This invention relates generally to semiconductor wafer and photomask alignment, and to fabrication of semiconductor wafers having alignment patterns which facilitate the same.
Photopatterning of semiconductive wafers requires precise positioning of a reticle or mask relative to the semiconductive wafer being processed. To achieve such precise positioning, the exact orientation or location of the wafer must be known such that the mask can be precisely placed. This is typically accomplished by moving the wafer beneath fixed optics which determine the wafer""s precise location relative to a table on which the wafer rests and moves relative to the optics. The optics are directed toward the wafer to determine location of predetermined patterns provided in the wafer at at least two discrete locations, such that wafer orientation is determined. With such known, the photomask and wafer can be precisely positioned in a desired relative orientation for processing.
The wafer alignment patterns typically include discrete areas on the semiconductor substrate which are initially patterned to form multiple series of precisely configured parallel lines. In subsequent processing of the wafer, sometimes these wafer alignment patterns are masked such that they are not subjected to the specific processing, while other times they are left unmasked and are accordingly processed. For example, in some instances it is desirable to provide a planarized layer of a highly reflective or opaque material. Such a layer, because it is planarized, would not repeat the underlying pattern and substantially all incident light would be reflected away or absorbed. In such instance, the underlying alignment pattern would be lost. Accordingly in such instances, the wafer alignment pattern area would not be masked such that etching of such materials would not occur over the alignment patterns.
Where planarization does not occur or where a planarized layer is suitably light transmissive to reveal the underlying pattern, the wafer alignment areas are typically masked during processing. Not masking of the wafer alignment pattern area throughout processing is typically not desired, as such would adversely effect overall global planarity of the wafer and eventually result in the wafer alignment patterns being received in deep holes or caverns. This would adversely effect the utility of the patterns and lead to other wafer processing problems. For example, whether an alignment step is masked or not masked during a photoexposure depends on several factors. These include, 1) the ability to see the alignment step at the next photo step; 2) the impact on the rest of the wafer, such as cracking and planarity; and 3) consistency in being able to get good alignment at all subsequent photosteps.
The increasing circuit density and vertical integration associated therewith has lead to increasing utilization of planarizing steps to assure an overall planar wafer which is easier to process. This, however, has placed difficult constraints upon photomask alignment relative to the wafers being processed. Specifically, contrasts provided by illuminating the wafer with incident light must rely in part upon differences in light intensity resulting from internal reflections off of a buried structure. This presents only minor problems for a single layer of surface planarized material, or for a stack of surface planarized transparent materials where each has a similar index of refraction and the underlying film has high reflectance. However where a stack of two planarized layers of different material having substantially different indexes of refraction is utilized, obtaining adequate contrast for ultimate wafer and photomask alignment becomes considerably more complex. An example is described below where a planar layer of polysilicon is provided over a surface planarized layer of oxide, with both such layers being provided over a silicon or silicide step in a wafer pattern alignment area.
The discussion initially proceeds with reference to FIGS. 1 and 2 illustrating a typical prior art wafer alignment pattern. FIGS. 1 and 2 illustrate a wafer alignment pattern indicated generally with reference numeral 10 patterned relative to a bulk monocrystalline silicon wafer 16. At least two of such patterns would be discretely located relative to the outer silicon wafer surface. Preferably, four of such discretely spaced patterns 10 are utilized. Wafer alignment pattern 10 is comprised of four discrete, or sub-discrete, alignment patterns 11, 12, 13 and 14. Wafer alignment pattern 10 is square, with each of sub-alignment patterns 11, 12, 13 and 14 also being square and located in one of the four quadrants of pattern 10. A central plus (+) 9 is centrally provided.
Each pattern 11, 12, 13 and 14 comprises a plurality of patterned elevation steps/valleys/lines 15 initially provided in the outer surface of silicon substrate 16. Accordingly, lands or valley 17 (FIG. 2) are provided between elevation steps 15. The wafer alignment patterns utilize substantially a same, common elevation step change xe2x80x9cAxe2x80x9d between lands 17 and 15 throughout all wafer alignment patterns on the wafer, with an example being 1000 Angstroms. Further, all of the elevation steps are provided at a substantially common average elevation relative to the wafer. Such is indicated in FIG. 2 with numeral 18 as the elevation within wafer 16 between lands 17 and outer portion of elevation steps 15.
FIG. 2 illustrates example subsequent layers deposited over wafer alignment pattern 10. Such include, for example, a conformal film 20, a planarized oxide layer 21, and an overlying planarized polysilicon layer 22. Both are suitably light transmissive to enable underlying topography to be perceived by laser light. Yet, the polysilicon of layer 22 has a substantially different refractive index from that of the oxide of layer 21. Depending upon the relative thicknesses of layers 21 and 22, this can create significant problems in achieving adequate contrast to determine underlying wafer pattern structure from steps 15 and lands 17. This results primarily from an undesired large quantity of light being reflected off the interface between planarized layers 21 and 22, as well as off the top of layer 22.
Inherent thicknesses of such layers can also be a significant factor in achieving adequate contrast. For example in some instances, there are thicknesses of polysilicon layer 22 where poor contrast is obtained for a given elevation step height between lands 17 and step 15 for any thickness of planar oxide layer 21. Selecting a better polysilicon thickness greatly improves the situation, but there still exists oxide thicknesses where very poor contrast is obtained.
Such is graphically apparent from FIG. 3. Such illustrates lines of constant reflectivity data as a function of thickness of a planarized polysilicon layer overlying a planarized oxide layer. Such data is relative to an underlying wafer alignment pattern having a 900 Angstrom elevation step change between lands 17 and peaks 15 and utilizing a 633 nanometer Hexe2x80x94Ne laser imaging system. Areas where low or unacceptable contrast is obtained for determining wafer pattern location is depicted in the hatch-shaded areas of the graph. On the other hand, high or acceptable contrast is generally obtained in those illustrated areas where the illustrated lines of constant reflectivity form self-enclosed rings or ovals.
For example, areas 24 and 25 run substantially continuously across or over the illustrated graph, and constitute planarized oxide and planarized silicon combinations where unacceptably low contrast would be obtained. Other areas, such as 26, 27 and 28, are discretely independently enclosed and evidence areas where good contrast is obtained for determining the underlying wafer alignment pattern.
As is apparent with this described example, planarized polysilicon thickness of, for example, 700 Angstroms and 1425 Angstroms result in poor contrast areas on the graph independent of oxide thickness. Accordingly in this example, the wafer processor would fundamentally avoid using planarized polysilicon layers of these thicknesses. The processor would rather attempt to operate in some other area of the depicted graph where adequate contrast is more likely. For example, for a polysilicon thickness of 1100 Angstroms, good example contrast is obtained for oxide thicknesses of between about 8625 Angstroms to about 9525 Angstroms. Yet, poor contrast would be obtained for such a polysilicon layer for oxide thicknesses of about 8500 Angstroms or about 8600 Angstroms.
A challenge facing the processor, however, is that the thickness of outer planarized polysilicon layer 22 is rather easy to control, whereas some underlying planarized layers such as oxide layer 21 are comparatively difficult to control. The processor can thereby avoid thicknesses of the outer layer which are inherently bad for any oxide thickness, but is left hoping that the less controllable underlying planarized layer doesn""t result in falling into an area of comparative thickness where contrast is less than adequate. Such would result in loss of an ability to determine location or existence of underlying wafer alignment pattern structure.
For example with the FIGS. 1 and 2 embodiment, oxide thickness needs to be controlled to better than 500 Angstroms to avoid a resultant inadequate contrast situation for the depicted prior art wafer alignment pattern structure. This is better control than can typically be expected, relying upon typical planarizing techniques.
Accordingly, it would be desirable to overcome or alleviate the above described problems to achieve improved contrast relative to wafer alignment patterns which is less dependent upon variable thickness of an underlying planarized layer.